The present invention relates to EEPROM cells. More particularly, the invention relates to biasing of dual row line EEPROM cells to reduce stress on the tunnel oxide window and improve the cell's reliability.
FIGS. 1A shows a perspective view of a typical EEPROM cell. The cell 30 is a single polysilicon EEPROM cell. As such, it does not have a polysilicon control gate, but instead has a heavily doped diffusion region in the cell's substrate which is capacitively coupled to its floating gate. The cell 30 is also a single row line EEPROM cell, since word line transistor (NI) and write column transistor (N3) are accessed via a single conductive connection, row line 31.
The cell 30 includes a single polysilicon floating gate structure 32 which performs three functions. At a first end, a tunnel extension 34 of floating gate 32 acts as an electrode in the two terminal device used for tunneling electrons from a heavily doped N.sup.+ implant 35 (also referred to as a programming Memory Diffusion or MD) through a tunnel oxide 36 (often about 80.ANG. thick) onto floating gate structure 32. At the other end of this floating gate, a wide area plate 38 is employed as one electrode of a capacitor enabling the floating gate 32 to be raised to a high voltage (e.g., about 6 to 11 volts) by capacitively coupling a programming voltage (e.g., about 9 to 13 volts) from a second electrode 40 (heavily doped N+ silicon, referred to herein as a control gate memory diffusion) through an oxide 42 (often about 180 .ANG. thick). Between these two ends is a section of polysilicon that forms the gate 44 of a read transistor (N2).
The read transistor (N2) is connected in series with a word line transistor (N1) having a gate 46 forming part of a word line (also referred to as a row line) 31. The read and word line transistors separate a sense amp negative (-) input 48 (a source line) from a sense amp positive (+) input 50 (a drain line). Charging the floating gate 32 by tunneling electrons onto it (through tunnel oxide 36) raises the threshold voltage of the read transistor (EEPROM cell 30 is programmed). This shuts off the channel between the sense amp inputs, even when the adjacent word line transistor is turned on. Tunneling electrons off the floating gate 32 reduces the read transistor threshold voltage to negative values, effectively turning this device on (EEPROM cell 30 is erased). The word line transistor in series then controls the signal path between the two sense amp inputs 48 and 50.
The EEPROM cell is programmed or erased by charging or discharging, respectively, the floating gate 32. In order to tunnel electrons onto floating gate 32, a high voltage must be applied to the control gate memory diffusion 40. At the same time, the write column 56 is grounded and the write column transistor (N3) is turned on by, for example, selecting the row line 31 with, for example, 5 volts. The sense amp (-) input 48 can be biased from 5 volts to a high voltage to assist tunneling electrons onto the floating gate 32. The voltage on the control gate memory diffusion 40 is capacitively coupled to the floating gate 32 as is the sense amp (-) input 48 voltage. The resulting positive voltage on floating gate 32 is sufficient to cause tunneling onto floating gate 32 through the tunnel dielectric window 36, thereby programming the EEPROM cell 30.
In order to tunnel electrons off floating gate 32, a high voltage must be applied to memory diffusion 35 while ground is applied to the second heavily doped N+ implant (control gate memory diffusion) 40 which underlies and is capacitively coupled to the wide area plate 38. During this process, ground is also applied to sense amp (-) input 48. The application of high voltage to memory diffusion 35 is accomplished through a write column 56 and a write column select transistor (N3) including (i) a diffusion region 54 conductively connected to write column 56 for data input, (ii) a source/drain diffusion 58 electrically connected to memory diffusion 35, and (iii) a gate electrode 60, which is part of row line 31. When a sufficient potential is applied to the gate 60 of the write column select transistor through row line 31 while a write signal is applied through write column 56, electrons can tunnel off of the floating gate 32 to erase the EEPROM cell.
FIGS. 1B and 1C depict a top view cell layout 100 and a circuit schematic 150 of the EEPROM cell of FIG. 1A, respectively. These depictions focus on cell elements important to the description of the present invention. FIG. 1B clearly shows a single row line 31, word line (N1) and write column (N3) transistors, write column 56 and control gate 38 in relation to the other cell elements previously described with reference to FIG. 1A.
A single row line cell, such as depicted in FIGS. 1A-C, cannot have its write column 56 and its drain line 50 voltages selected separately. As a result, transistors (N1) and (N3) are either both on or both off at any given time depending on whether the row line 31 is selected. During normal operation of the cell, the selection of the row line 31 is under the control of the user. Therefore the manufacturer of a single row line EEPROM cell cannot attribute a fixed setting to the write column terminal 56 and have that bias passed down to the memory diffusion 35 (FIG. 1C) through the transistor (N3). Since voltage on the write column 56 cannot pass through to the programming memory diffusion 35 under the tunnel window 36 when the write column transistor (N3) is off, it is not possible to maintain a steady positive voltage on the memory diffusion 35 during normal operation when word line (drain line) transistor (N1) may be on or off. As a result, the write column is typically grounded (about 0 V) during normal operation of a single row line EEPROM cell in order to maintain the voltage on the memory diffusion (and therefore across the tunnel window when the control gate voltage is fixed) as steady as possible and thereby reduce stress in the cell.
Dual row line EEPROM cells are also known in the art. A top view cell layout and a circuit schematic of a single polysilicon dual row line EEPROM cell is shown in FIG. 2A. The cell 200 has two separate word lines (row lines) 202 and 204 for accessing its drain line and write column, respectively. Otherwise, a typical dual row line EEPROM cell has its remaining elements in common with a single row line EEPROM cell, such as that described above.
In a conventional biasing scheme based on the single row line cell, electrons are tunneled onto the floating gate 32 of a dual row line EEPROM cell by applying a high voltage to the control gate memory diffusion 40. At the same time, the write column 56 is grounded and the write column select line 202 is selected with, for example, 5 volts. The sense amp (-) input 48 can be biased to a positive voltage to assist tunneling electrons onto the floating gate 32. The voltages on the control gate memory diffusion 40 and the sense amp (-) input 48 are capacitively coupled to the floating gate 32. The resulting positive voltage on floating gate 32 is sufficient to cause tunneling onto floating gate 32 through the tunnel dielectric window 36, thereby programming the EEPROM cell 200.
In order to tunnel electrons off floating gate 32 of a dual row EEPROM cell, a high voltage must be applied to memory diffusion 35 while ground is applied to the control gate memory diffusion 40. During this process, ground may also be also applied to sense amp (-) input 48. The application of high voltage to memory diffusion 35 is accomplished through the write column 56 and a write column select transistor (N3) including (i) a diffusion region 54 conductively connected to write column 56 for data input, (ii) a source/drain diffusion 58 electrically connected to memory diffusion 35, and (iii) a gate electrode 60, which is part of a second row line 204. When a sufficient potential is applied to the gate 60 of the write column select transistor through the write column select line (second row line) 204, while a write signal is applied through write column 56, electrons can tunnel off of the floating gate 32 to erase the EEPROM cell.
It should be noted that EEPROM cells may also be formed by a double polysilicon process. Such a "double poly" EEPROM cell has a polysilicon control gate capacitively coupled to its floating gate. As will be readily understood by those of skill in the art from the description below, the present invention is also applicable to double poly EEPROM cells.
A further description of a typical EEPROM cell and its functional elements is available the publication "EPM7032 Process, Assembly, and Reliability Information Package" available from Altera Corporation of San Jose Calif. That document is incorporated herein by reference for all purposes.
In order for an MOS transistor to conduct, the voltage on its gate must overcome (be greater than) the transistor's threshold voltage (V.sub.th). Generally, the threshold voltage is that gate voltage required to create an inversion layer in the transistor's channel so that it conducts. When the MOS transistor is part of a programmable bit of memory, such as an EEPROM cell, there are two gates: The floating gate and the control gate. Such a cell will have two threshold voltages, corresponding to each of its programmed and erased states. The floating gate voltage required to invert the transistor (V.sub.th) does not change for a given cell, but the control gate voltage to invert the transistor (that is, to bring the floating gate to V.sub.th) differs depending upon the charged or discharged state of the cell.
Prior to shipping an EEPROM memory cell product, a manufacturer will generally test the cells to guarantee that a each bit of memory has a good margin, and that the bit will maintain its programmed or erased state over the lifetime of the cell. The "margin" is the voltage required on a cell's control gate to cause a change in the state of a bit of memory. Since a programmable cell has two threshold voltages, it will have two margin voltages: One for the programmed state and one for the erased state. In an EEPROM cell, an erased bit will have a lower margin voltage, typically between about -5V to 0V, and a programmed bit will typically have a higher margin voltage, typically between about 3 V and 8 V. In normal cell operation, an EEPROM's control gate will conventionally be set at a value between the programmed and erased ranges, for example about 1.7 V.
Conventionally, the same biasing scheme has been used in both single and dual row line EEPROM cells. As a result, in both cases, the potential difference between the control gate and the write column is about the same as the voltage on the control gate, e.g., 1.7 V.
One potential problem with EEPROM cells is that the charge on a programmed floating gate is subject to charge retention problems arising from stress-induced leakage current (SILC) through the tunnel dielectric. A contributor to SILC in such a conventionally biased cell is charge trapping in the tunnel oxide during the cell's program and erase cycles. When a cell is programmed and erased, electrons move to and from the floating gate through the tunnel dielectric. These electrons can create "traps" in the oxide (i.e., electrons are trapped in the oxide). The trap density increases with the number of program and erase cycles seen by the tunnel dielectric. Due to the presence of these traps, a programmed or erased floating gate may show an enhanced charge loss or charge gain under low electric fields across the tunnel dielectric commonly seen during normal operating conditions of the cell. Such low level charge loss and charge gain mechanisms are undesirable since EEPROM devices need to have about a ten-year lifetime to be practical in most user environments. As chip designers allow In System Programming (ISP) capabilities to the user, the number of program and erase cycles used will increase, adding more pressure on immunity from charge retention problems due to SILC leakages.
Since the user can store a device unpowered on the shelf, or use the device on a system board fully powered, a chip supplier needs to guarantee both programmed and erased bit charge retention under both modes of operation. The electric fields across the tunnel dielectrics differ between the two modes for both programmed and erased bits. As a result, the worst case condition acts as the dominating field to ensure immunity to SILC leakages. A technique to balance and reduce these fields would be beneficial to guarantee margins for SILC.
Changes in EEPROM cell design may affect the amount of stress on the tunnel window and increase the likelihood of SILC problems. For example, patent application Ser. No. 08/995,873 (Attorney Docket No. ALTRP022), which is incorporated herein by reference for all purposes, discloses process and circuit changes to EEPROM cells which increase a cell's threshold voltage, and in turn increase the cell's margin voltage. Increasing the margin voltage increases the potential that will be applied across the cell's tunnel window during margin testing, which renders the possibility of an SILC more likely.
Accordingly, a way of biasing dual row line EEPROM cells which would reduce the stress on a cell's tunnel dielectric window would be desirable.